Changelog for cpuid-20230614-2.5.x86_64.rpm :

* Wed Jun 21 2023 Valentin Lefebvre - Update to release 20230614
* Improved (synth) identification for Intel Xeon Scalable (3rd Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D), Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100 Arizona Beach.
* Made the (simple synth) fields non-default. The (simple synth) fields still are available, but only with the -S/--simple option.- Update to release 20230505
* Fixed CPU counts for higher levels not dividing out counts from lower levels.
* Differentiate Core i3-N300 N-Series from ordinary N-Series.
* Added hypervisor+4/eax bit 21: use hypercalls for MMIO config space I/O, based on LX
*.
* Added (synth) decoding for Xeon W version of Sapphire Rapids, Meteor Lake-M B0.
* Added (synth) & (uarch synth) Emerald Rapids family: Raptor Cove, and Granite Rapids family: Redwood Cove.
* Fri Apr 14 2023 Egbert Eich - Update to release 20230406:
* Support APIC bit fields for the newest 4 topology layers: module, tile, die, die group.
* Support leaf 0xb method for AMD/Hygon.
* Added prelim Bergamo A1 stepping from sample.
* Added AMX-COMPLEX instructions, UC-lock disable, non-contiguous 1s value support, event logging supported bitmap.
* Update CPUID utility with new feature bits as documented in the AMD Processor Programming Reference for Family 19h and Model 11h: extended LVT offset fault cange, enhanced predictive store forwarding, FSRS, FSRC, FsGsKernelGsBaseNonSerializing, number of available UMC PMCs, bitmask representing active UMCs.
* Added (synth) decoding for Sapphire Rapids D & E0 steppings
* Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for Raptor Lake-H/U/P.
* Differentiate (synth) & (uarch synth) for (0,6),(11,14) Alder Lake-N based on core type.
* Differentiate Lakefield P-cores from Tremont E-cores.
* Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
* Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
* Added PkgType decoding for AMD Family 19h CPUs: Vermeer, Cezanne/Barcelo, Raphael, and Phoenix, based on their respective PPPRs.
* Added Alder Lake Core names: i
*-12000.
* Decode Xen tsc mode.
* Sat Jan 28 2023 Dirk Müller - updated to 20230120:
* Intel\'s 13th Generation Core datasheet provides stepping names as well as numbers! So:
* cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
* cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0 steppings, and clarified case for unknown stepping.
* cpuid.man: Added 743844: 13th Generation Core datasheet.
* cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
* cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
* cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
* cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
* cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
* cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
* cpuid.c: Added several 7/2/edx bits.
* cpuid.c: In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS.
* cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren\'t relevant for XCR0.
* cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a hex bitmask.
* cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
* cpuid.c: Renamed 0x1a: Native Model ID.
* cpuid.c: Added synth & uarch decoding for (0,6),(11,15) Raptor Lake from MSR_CPUID_table
*.
* cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400, based on instlatx64 sample.
* cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15) Emerald Rapids CPUs.
* cpuid.c: Added 7/1/eax LASS: linear address space separation.
* cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which should use minus-one notation.
* cpuid.c: Certain leaves cannot be displayed correctly in isolation, i.e. without information about other leaves saved in the stash. For example, the display for leaf 3 uses bits saved from leaf 1. If the - l/--leaf option is used to restrict cpuid to reading only a single leaf, such leaves now are displayed as raw hex, rather than with incorrect information. This is handled by passing a NULL stash to print_reg() and below, and by many new checks for a NULL stash.
* cpuid.c: Updated cache associativity strings used in 0x80000006 and 0x80000019 leaves to use value ranges, as in AMD docs.
* cpuid.c: Fixed mistake in AMD L3 range reservation support: it\'s in 0x80000020/0 register EBX, not ECX.
* cpuid.c: Added 0x80000026/0/edx extended APIC ID.
* cpuid.c: Added synth & uarch decoding for (10,15),(1,1) Genoa, from AMD 57095 revision guide.
* cpuid.man: Added AMD 57095 revision guides, and some older guides that I\'d forgotten.
* Mon Dec 05 2022 Valentin Lefebvre - Update to release 20221201
* Clarified synth decoding for Intel Xeon D-1700.
* Added uarch & synth decoding for AMD 4800S Desktop Kit, based on instlatx64 sample.
* Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
* Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX
*.
* Added synth & uarch decoding for (10,15),(10,1) Bergamo.
* Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
* Added 0x8000001b/eax bit: IBS L3 miss filtering support.
* Added 0x8000001f/eax bits: RMPQUERY instruction support, VMPL supervisor shadow stack support, VMGEXIT parameter support, virtual TOM MSR support, IBS virtual support for SEV-ES guests, SMT protection support, SVSM communication page MSR support, VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
* Added 0x80000020/0/ecx bit: L3 range reservation support.
* Added 0x80000021/eax bits: automatic IBRS, CPUID disable for non-privileged.
* Added 0x80000022/eax bit: AMD LBR & PMC freezing.
* Added 0x80000022/ebx field: number of LBR stack entries.
* Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
* Added 0x80000026 leaf: AMD Extended CPU Topology.
* cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax AMD LBR V2 flag, from LX
*.
* Thu Oct 13 2022 Valentin Lefebvre - Update to release 20221003
* Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
* Added synth & uarch synth decoding for
* (0,6),(11,5) Intel Meteor Lake
* (0,6),(11,6) Intel Grand Ridge (Crestmont)
* (0,6),(11,14) Intel Granite Rapids
* Renamed 7/0/eax enh hardware feedback to just \"Thread Director\".
* Added 7/1/eax instructions.
* Added 0x12/0/eax SGX ENCLU EDECCSA flag.
* Added 0x23 Architecture Performance Monitoring Extended leaf decoding.
* Corrected AVX512IFMA description: integer FMA, not just FMA.- Release 20220927
* Added synth decoding for (10,15),(6,1) Raphael
* Fixed title for AMD 0x8000001a leaf: Performance Optimization identifiers.
* Sat Aug 13 2022 Jan Engelhardt - Update to release 20220812
* Corrected (synth) decoding for (0,6),(8,6) Intel Snow Ridge/Parker Ridge.
* Added 8000000a/edx X2AVIC flag
* Generalized (0,6),(8,14),9,YP stepping case to include Pentium 4425Y, from instlatx64 sample.
* Added support for hypervisor+3/ecx (Microsoft) flags.
* Thu Feb 24 2022 Andreas Stieger - update to 20220224:
* Support for AMD Rembrandt E1
* Add hypervisor+4/eax (Xen) expanded destination id bit
* Correction for Alder Lake, Rocket Lake decoding
* Multiple detection and decodings updated
* Mon Nov 15 2021 Andreas Stieger - update to 20211114:
* Many updated and added identified CPU models and variants
* Updated hypervisor support
* Thu Oct 08 2020 Josef Möllers - Update to 20201006: Added \"Sapphire Rapids\", \"Golden Cove\", \"Rocket Lake\", \"Cato\", 14nm \"Zen\", \"Tiger Lake-U B0\", \"Elkhart Lake B0\", \"Alder Lake\", \"Comet Lake\", \"Picasso A1\", \"Renoir A1\", \"Zhaoxin KaiXian KX-6000\", as well as some additional decoding of supported features. [cpuid-20201006.src.tar.gz, jsc#sle-13189]
* Tue Apr 28 2020 Andreas Stieger - update to 20200427:
* Add synth decoding for AMD Steppe Eagle/Crowned Eagle (Puma 2014 G-Series), based on instlatx64 sample
* Add 7/0/edx SERIALIZE & TSXLDTRK bit descriptions
* Add 0xf/1/eax Counter width & overflow flag
* Add 0x10/3/ecx per-thread MBA controls flag
* Add 0x8000001f fields
* Add AMD 24594 & 40332 docs
* Correct field lengths in 14/0 and 14/1 subleafs so that columns line up
* Add CC150 (Coffee Lake R0) synth decoding, based on instlatx64 example
* Add Jasper Lake A0 stepping (from Coreboot
*)
* Update 1/ebx \"cpu count\" to modern terminology: \"maximum addressible IDs for CPUs in pkg\" to avoid user confusion
* Update 4/eax CPU & core count terminology in the same way