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perl-Verilog-CodeGen rpm build for : Fedora 26. For other distributions click perl-Verilog-CodeGen.

Name : perl-Verilog-CodeGen
Version : 0.9.4 Vendor : Fedora Project
Release : 22.fc26 Date : 2017-02-11 16:58:36
Group : Development/Libraries Source RPM : perl-Verilog-CodeGen-0.9.4-22.fc26.src.rpm
Size : 0.07 MB
Packager : Fedora Project
Summary : Verilog code generator
Description :
Provides an object-oriented environment to generate Verilog code for
modules and testbenches. The Verilog::CodeGen module provides two
functions, one to create a code template and another to create a Perl
module which contains the device library. This module ,
DeviceLibs::YourDesign, provides the class methods and contains the objects
for every Verilog module; the objects are created based on a fixed
template. The purpose of this module is to allow the generation of
customized Verilog modules. A Verilog module can have a large number of
parameters like input and output bus width, buffer depth, signal delay etc.
The code generator allows to create an object that will generate the
Verilog module code for arbitraty values of the parameters.

RPM found in directory: /packages/linux-pbone/archive.fedoraproject.org/fedora-secondary/releases/26/Everything/ppc64le/os/Packages/p

Content of RPM  Changelog  Provides Requires

Download
ftp.icm.edu.pl  perl-Verilog-CodeGen-0.9.4-22.fc26.noarch.rpm
ftp.icm.edu.pl  perl-Verilog-CodeGen-0.9.4-22.fc26.noarch.rpm
     

Provides :
perl(Verilog::CodeGen)
perl(Verilog::CodeGen::Gui)
perl-Verilog-CodeGen

Requires :
dia
gtkwave
iverilog
perl(:MODULE_COMPAT_5.24.1)
perl(Cwd)
perl(sigtrap)
perl(strict)
perl(vars)
rpmlib(CompressedFileNames) <= 3.0.4-1
rpmlib(FileDigests) <= 4.6.0-1
rpmlib(PayloadFilesHavePrefix) <= 4.0-1
rpmlib(PayloadIsXz) <= 5.2-1
tkgate
xemacs


Content of RPM :
/usr/share/doc/perl-Verilog-CodeGen
/usr/share/doc/perl-Verilog-CodeGen/Changes
/usr/share/doc/perl-Verilog-CodeGen/README
/usr/share/doc/perl-Verilog-CodeGen/scripts
/usr/share/doc/perl-Verilog-CodeGen/scripts/GUI
/usr/share/doc/perl-Verilog-CodeGen/scripts/GUI/create_design.pl
/usr/share/doc/perl-Verilog-CodeGen/scripts/GUI/debug.pl
/usr/share/doc/perl-Verilog-CodeGen/scripts/GUI/inspect_code.pl
/usr/share/doc/perl-Verilog-CodeGen/scripts/GUI/rectangle_power_perl.gif
/usr/share/doc/perl-Verilog-CodeGen/scripts/GUI/send_stdout.pl
/usr/share/doc/perl-Verilog-CodeGen/scripts/GUI/test.pl
/usr/share/doc/perl-Verilog-CodeGen/scripts/GUI/update.pl
/usr/share/doc/perl-Verilog-CodeGen/scripts/gui.pl
/usr/share/man/man3/Verilog::CodeGen.3pm.gz
/usr/share/man/man3/Verilog::CodeGen::Gui.3pm.gz
/usr/share/perl5/vendor_perl/Verilog
/usr/share/perl5/vendor_perl/Verilog/CodeGen
/usr/share/perl5/vendor_perl/Verilog/CodeGen.pm
/usr/share/perl5/vendor_perl/Verilog/CodeGen/Gui.pm

 
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