| Name : ghc-clash-systemverilog
| |
| Version : 0.6.10
| Vendor : obs://build_opensuse_org/devel:languages:haskell
|
| Release : 2.16
| Date : 2018-01-23 23:16:17
|
| Group : Development/Languages/Other
| Source RPM : ghc-clash-systemverilog-0.6.10-2.16.src.rpm
|
| Size : 0.69 MB
| |
| Packager : (none)
| |
| Summary : CAES Language for Synchronous Hardware - SystemVerilog backend
|
Description :
CλaSH (pronounced ‘clash’) is a functional hardware description language that
borrows both its syntax and semantics from the functional programming language
Haskell. The CλaSH compiler transforms these high-level descriptions to
low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of CλaSH:
* Strongly typed (like VHDL), yet with a very high degree of type inference,
enabling both safe and fast prototying using consise descriptions (like
Verilog).
* Interactive REPL: load your designs in an interpreter and easily test all
your component without needing to setup a test bench.
* Higher-order functions, with type inference, result in designs that are fully
parametric by default.
* Synchronous sequential circuit design based on streams of values, called
\'Signal\'s, lead to natural descriptions of feedback loops.
* Support for multiple clock domains, with type safe clock domain crossing.
This package provides:
* SystemVerilog Backend.
|
RPM found in directory: /packages/linux-pbone/ftp5.gwdg.de/pub/opensuse/repositories/devel:/languages:/haskell:/lts:/7/openSUSE_Leap_42.2/x86_64 |
Hmm ... It's impossible ;-) This RPM doesn't exist on any FTP server
Provides :
ghc-clash-systemverilog
ghc-clash-systemverilog(x86-64)
libHSclash-systemverilog-0.6.10-KHKN7q0v46n1UzTgT0jssu-ghc8.0.1.so()(64bit)
Requires :
