| Name : verilator
| |
| Version : 4.106.1606957763.b350b6a0
| Vendor : obs://build_opensuse_org/hardware
|
| Release : fpga.1.2
| Date : 2024-06-03 16:30:29
|
| Group : Productivity/Scientific/Electronics
| Source RPM : verilator-4.106.1606957763.b350b6a0-fpga.1.2.src.rpm
|
| Size : 17.62 MB
| |
| Packager : https://www_suse_com/
| |
| Summary : Compiling Verilog HDL simulator
|
Description :
Verilator compiles synthesizable Verilog (not test-bench code), plus
some PSL, SystemVerilog and Synthesis assertions into an optimized
model which is in turn wrapped inside a C++/SystemC module for faster
execution.
|
RPM found in directory: /packages/linux-pbone/ftp5.gwdg.de/pub/opensuse/repositories/hardware:/FPGA/15.5/x86_64 |
