| Name : verilator
| |
| Version : 1701880342.a09f771
| Vendor : obs://build_opensuse_org/home:leviathanch
|
| Release : 23.18
| Date : 2017-02-16 11:56:03
|
| Group : Productivity/Scientific/Electronics
| Source RPM : verilator-1701880342.a09f771-23.18.src.rpm
|
| Size : 20.14 MB
| |
| Packager : (none)
| |
| Summary : Compiling Verilog HDL simulator
|
Description :
Verilator compiles synthesizable Verilog (not test-bench code), plus
some PSL, SystemVerilog and Synthesis assertions into an optimized
model which is in turn wrapped inside a C++/SystemC module for faster
execution.
|
RPM found in directory: /packages/linux-pbone/ftp5.gwdg.de/pub/opensuse/repositories/home:/leviathanch:/asic/openSUSE_Tumbleweed/x86_64 |
